Design of low error CSD fixed-width multiplier

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Kim, Sang Min ^a   Chung, Jin Gyun ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; ERROR COMPENSATION; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PROBABILITY;

CANONIC SIGNED DIGIT; ERROR COMPENSATION BIAS CIRCUIT; QUANTIZATION ERROR; TRUNCATED BITS;

MULTIPLYING CIRCUITS;

EID: 0036286885     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Area-efficient multipliers for digital signal processing applications
2. Design of a low-error fixed-width multiplier for DSP applications
3. Design of the lower error fixed-width multiplier and its application
4. Fixed-width multiplier for DSP application
5. Sign extension reduction by propagated-carry selection