Sign extension reduction by propagated-carry selection

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2001, Pages 134-138

  Kim, Sang Min ^a   Chung, Jin Gyun ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENCODING (SYMBOLS); MULTIPLYING CIRCUITS; POWER SUPPLY CIRCUITS; VECTOR QUANTIZATION;

CANONIC SIGNED DIGIT; CARRY PROPAGATION; COMPENSATION VECTOR; SIGN EXTENSION REDUCTION;

CARRY LOGIC;

EID: 0035574196     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Binary arithmetic
2. Area-efficient multipliers for digital signal processing applications
3. Design of a low-error fixed-width multiplier for DSP applications
4. Design of the lower error fixed-width multiplier and its application