A generalized methodology for lower-error area-efficient fixed-width multipliers

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages 65-68

  Van, Lan Da ^a   Lee, Sung Huang ^a  

^a National Science Council   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR ANALYSIS; ERROR COMPENSATION; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; STATISTICAL METHODS; VLSI CIRCUITS;

BAUGH-WOOLEY ALGORITHM; TRUNCATION ERROR;

MULTIPLYING CIRCUITS;

EID: 0036286695     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1009778     Document Type: Article

References (9)

1. A two's complement parallel array multiplication algorithm
2. Single-precision multiplier with reduced circuit complexity for signal processing applications
3. Truncated multiplication with correction constant
4. Area-efficient multipliers for digital signal processing applications
5. Data-dependent truncation scheme for parallel multipliers
6. Truncated multiplication with approximate rounding
7. Design of low-error fixed-width multiplier for DSP applications
8. Design of the lower-error fixed-width multiplier and its application