Analytical, transistor-level energy model for SRAM-based caches

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1999, Pages

  Bellas, Nikos ^a   Hajj, Ibrahim ^a   Polychronopoulos, Constantine ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STATIC RANDOM ACCESS MEMORY (SRAM);

COMPUTER SIMULATION; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE;

BUFFER STORAGE;

EID: 0032670604     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (7)

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7. N. Bellas, I. Hajj, C. Polychronopoulos, and G. Stamoulis, "Architectural and compiler support for energy reduction in the memory hierarchy of high performance micro processors," in Proceedings of the International Symposium of Low Power Electronics and Design, pp. 70-75, Aug, 1998.