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1
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25744438068
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An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7-1.4V
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paper 11.6
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S. Thompson, et al., "An Enhanced 130 nm Generation Logic Technology Featuring 60 nm Transistors Optimized for High Performance and Low Power at 0.7-1.4V," Digest of IEDM 2001, paper 11.6
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Digest of IEDM 2001
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Thompson, S.1
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2
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0033325117
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Device issues in the integration of analog/RF functions in deep sub-micron digital CMOS
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Dennis Buss, "Device Issues in the Integration of Analog/RF Functions in Deep Sub-micron Digital CMOS," Digest of IEDM 1999, p.423
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Digest of IEDM 1999
, pp. 423
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Buss, D.1
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3
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0242593439
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State of the art RF/analog foundry technology
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paper 22.1
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Jason C.H. Lin, et al., "State of the Art RF/Analog Foundry Technology," Digest of BCTM 2002, paper 22.1
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Digest of BCTM 2002
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Lin, J.C.H.1
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5
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85070027832
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2 gate dielectric and polysilicon damascene gate
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paper 17.1
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2 Gate Dielectric and Polysilicon Damascene Gate," Dig. Of IEDM 2002, paper 17.1
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Dig. of IEDM 2002
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Tavel, B.1
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6
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0008851540
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Distributed active transformer - A new power-combining and impedance-transformation technique
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Jan.
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I. Aoki, S. D. Kee, D. Rutledge, A. Jajimiri, "Distributed Active Transformer - A New Power-combining and Impedance-Transformation Technique.", IEEE Trans. On Microwave Theory and Techniques. P316, Jan. 2002.
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(2002)
IEEE Trans. on Microwave Theory and Techniques
, pp. 316
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Aoki, I.1
Kee, S.D.2
Rutledge, D.3
Jajimiri, A.4
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7
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22544477781
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A 9uW 50MHz 32b adder using a self-adjusted forward body bias in SoCs
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paper6.8
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K. Ishibashi, "A 9uW 50MHz 32b Adder using a self-adjusted forward body bias in SoCs," Dig. Of ISSCC 2003, paper6.8, p. 116
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Dig. of ISSCC 2003
, pp. 116
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Ishibashi, K.1
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8
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0036927963
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SiGe HBTs with cut-off frequency of 350GHz
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paper 31.3
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J.-S. Rich, et al., "SiGe HBTs with Cut-off Frequency of 350GHz," Digest of IEDM2002, paper 31.3
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Digest of IEDM2002
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Rich, J.-S.1
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9
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0036923796
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Ultra-high-speed scaled-down self-aligned SEG SiGe HBTs
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paper 31.2
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K. Washio, et al., "Ultra-High-Speed Scaled-down Self-Aligned SEG SiGe HBTs," Digest of IEDM 2002, paper 31.2
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Digest of IEDM 2002
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Washio, K.1
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10
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0036930469
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Sub 5 ps SiGe bipolar technology
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paper 31.1
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J. Bock, et al., "Sub 5 ps SiGe Bipolar Technology," Digest of IEDM 2002, paper 31.1
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Digest of IEDM 2002
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Bock, J.1
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11
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0036927966
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A flexible, low-cost, high performance SiGe:C BiCMOS process with a one-mask HBT module
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paper 31.5
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D. Knoll, et al., "A Flexible, Low-Cost, High Performance SiGe:C BiCMOS Process with a One-Mask HBT Module," Digest of IEDM 2002, paper 31.5
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Digest of IEDM 2002
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Knoll, D.1
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13
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18344405850
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0.1 μm RFCMOS on high resistivity substrates for system on chip (SoC) applications
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paper 27.8
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J.-Y. Yang et al., "0.1 μm RFCMOS on high Resistivity Substrates for System on Chip (SoC) Applications," Digest of IEDM 2002, paper 27.8
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Digest of IEDM 2002
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Yang, J.-Y.1
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14
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0242593447
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Private communications, Dr. C.T. Yang
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Private communications, Dr. C.T. Yang.
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15
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0036049043
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A porous Si based novel isolation technology for mixed-signal integrated circuits
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paper 16.3
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H.-S. Kim, et al., "A Porous Si Based Novel Isolation Technology for Mixed-signal Integrated Circuits," Dig. Symp. Of VISI Technology 2002, p.160, paper 16.3
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Dig. Symp. of VISI Technology 2002
, pp. 160
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Kim, H.-S.1
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16
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0036045163
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Improvement of high resistivity substrate for future mixed analog-digital applications
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paper 16.2
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T. Ohguro, et al., "Improvement of High Resistivity Substrate for Future Mixed Analog-Digital Applications," Dig. Symp. Of VLSI Technology 2002 p.158, paper 16.2
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Dig. Symp. of VLSI Technology 2002
, pp. 158
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Ohguro, T.1
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17
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0035340555
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Isolation of Si wafers by Mev proton bombardment for RF integrated circuits
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May
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L.S. Lee, C. Liao, C.L. Lee, T.H. Huang, D.L. Tang, T.S. Duh, and T.T. Yang "Isolation of Si wafers by Mev proton bombardment for RF integrated circuits," IEEE Trans. Electron Devices Tech., vol. 48, pp. 928-934, May 2001.
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(2001)
IEEE Trans. Electron Devices Tech.
, vol.48
, pp. 928-934
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Lee, L.S.1
Liao, C.2
Lee, C.L.3
Huang, T.H.4
Tang, D.L.5
Duh, T.S.6
Yang, T.T.7
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18
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0242593448
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Characterization and model of high quality factor and broadband integrated inductor on Si-substrate
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submitted for publication
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M. T. Yang, et al., "Characterization and Model of High Quality Factor and Broadband Integrated Inductor on Si-Substrate," submitted for publication
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-
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Yang, M.T.1
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19
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0036923873
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High capacitance Cu/Ta2O5/Cu MiM structure for SoC applications featuring a single mask add-on process
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paper 9.7
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T. Ishikawa, D. Kodama, Y. Matsui, "High Capacitance Cu/Ta2O5/Cu MiM Structure for SoC Applications Featuring a single Mask add-on Process," Digest of IEDM 2002, paper 9.7
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Digest of IEDM 2002
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Ishikawa, T.1
Kodama, D.2
Matsui, Y.3
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