Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 635-638

  Choi, Jin Hyeok ^a   Sakurai, Takayasu ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; REDUCED INSTRUCTION SET COMPUTING;

BLOCK ACTIVATION PROBABILITY; ON-CHIP MEMORY; STATISTICAL LEAKAGE CURRENT REDUCTION; ZIGZAG SUPER CUT-OFF SCHEME;

LEAKAGE CURRENTS;

EID: 0242443631     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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