Efficient gate clustering for MTCMOS circuits

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 34-38

  Anis, Mohab H ^a   Mahmoud, Mohamed K ^a   Elmasry, Mohamed I ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; ELECTRONICS PACKAGING; GRAPH THEORY; LOGIC GATES; MATHEMATICAL MODELS; RESISTORS; THRESHOLD VOLTAGE;

DEEP SUBMICRON; GATE CLUSTERING; SET PARTITIONING PROBLEM; SLEEP TRANSISTOR; VOLTAGE DROP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034782017     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2001.954669     Document Type: Article

References (6)

1. 1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
2. MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
3. Transistor sizing issues and tool for multithreshold CMOS technology
4. Technology for advanced high-performance microprocessors
5. Knapsack problems; algorithms and computer implementations
6. Solving set partitioning problems with constraint programming