Timed test generation for crosstalk switch failures in domino CMOS

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 379-385

  Kundu, R ^a   Blanton, R D ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Circuit testing; Clocks; Coupling circuits; Crosstalk; Latches; Logic testing; MOSFETs; Switches; Switching circuits; Timing

Indexed keywords

CHOPPERS (CIRCUITS); CLOCKS; CROSSTALK; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MICROSTRIP LINES; SWITCHES; SWITCHING CIRCUITS; TESTING; TIMING CIRCUITS; VLSI CIRCUITS;

CAPACITIVE COUPLINGS; CAPACITIVELY COUPLED; CIRCUIT TESTING; DOMINO LOGIC CIRCUITS; LOGIC TESTING; MOSFETS; OUTPUT TRANSITION; TIMING;

COUPLED CIRCUITS;

EID: 0142206125     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011168     Document Type: Conference Paper

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