Timing verification of sequential domino circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 127-132

  Van Campenhout, David ^a   Mudge, Trevor ^a   Sakallah, Karem A ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; ELECTRIC NETWORK ANALYSIS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS;

SEQUENTIAL DOMINO CIRCUITS; STATIC TIMING VERIFICATION;

SEQUENTIAL CIRCUITS;

EID: 0030418924     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)