Switch-level delay test of domino logic circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 367-376

  Natarajan, Suriyaprakash ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; INTEGRATED CIRCUIT TESTING; LOGIC GATES;

DOMINO CIRCUITS;

LOGIC CIRCUITS;

EID: 0035687654     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Synthesis of delay-verifiable combinational circuits
2. Critical path identification and delay tests of dynamic circuits
3. On delay fault testing in logic circuits
4. Robust path delay-fault testability on dynamic CMOS circuits
5. Switch-level delay test
6. Model for delay faults based on paths
7. Universal delay test sets for logic networks