XIDEN: Crosstalk target identification framework

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 365-374

  Nazarian, Shahin ^a   Huang, Hang ^a   Natarajan, Suriyaprakash ^a   Gupta, Sandeep K ^a   Breuer, Melvin A ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CROSSTALK; ELECTRIC FILTERS; ERRORS; FUNCTIONS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; THEOREM PROVING; VLSI CIRCUITS;

BOOLEAN ERRORS; CROSSTALK TARGET IDENTIFICATION FRAMEWORK; EXTRACTORS; STEP FUNCTION;

INTEGRATED CIRCUIT TESTING;

EID: 0036444497     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. W.Y. Chen, S.K. Gupta and M.A. Breuer, "Analytic models for crosstalk delay and pulse analysis for non-ideal inputs," Proc. Int'l Test Conf., pp. 809-818, 1997.
2. W.Y. Chen, S.K. Gupta and M.A. Breuer, "Test generation for crosstalk-induced faults: framework and computational results," Proc. Asian Test Symp., pp. 305-310, 2000.
3. M.A. Margolese and F.J. Ferguson, "Using temporal constraints for eliminating crosstalk candidates for design and test", Proc. VLSI Test Symp., pp. 80-85, 1999.
4. K.J. Keller, H. Takahashi, K.K. Saluja and Y. Takamatsu. "On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits," Proc. Int'l Test Conf., pp. 568-577, 2001.
5. M.A. Breuer and S.K. Gupta, "Process aggravated noise (PAN): new validation and test problems," Proc. Int'l Test Conf., pp. 914-923, 1996.
6. W.Y. Chen, S.K. Gupta, and M.A. Breuer, "Test generation for crosstalk-induced delay integrated circuits", Proc. Inte'l Test Conf., pp. 191-200, 1999.
7. S. Natarajan, M.A. Breuer and S.K. Gupta, "Process variations and their impact on circuit operation", Int'l Symp. On Defects and Fault Tolerance in VLSI Systems, pp. 73-81, 1998.
8. D. Sylvester, C. Hu, O.S. Nakagawa and S.Y. Oh. "Interconnect scaling: signal integrity and performance in future high-speed CMOS designs," Digest of Papers of the Symp. On VLSI Technology, pp. 42-43, 1998.
9. W.Y. Chen, S.K. Gupta, M.A. Breuer, "Test generation for crosstalk-induced faults: framework and computational results," J. Electronic Testing: Theory and Applications (JETTA), vol. 18. no. 1, pp. 17-28, Feb. 2002.