Dynamic noise analysis in precharge-evaluate circuits

Proceedings-Design Automation Conference

Volumn , Issue , 2000, Pages 243-246

  Somasekhar, Dinesh ^a   Choi, Seung Hoon ^a   Roy, Kaushik ^a   Ye, Yibin ^b   De, Vivek ^b  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER AIDED ANALYSIS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; CROSSTALK; LOGIC CIRCUITS; LOGIC GATES; VLSI CIRCUITS;

DYNAMIC NOISE ANALYSIS; PRECHARGE EVALUATE CIRCUITS;

SPURIOUS SIGNAL NOISE;

EID: 0033714216     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2000.855311     Document Type: Article

References (8)

1. A. P. Chandrakasan R. Allmon A. Stratakos R. W. Brodersen Design of portable systems IEEE Custom Integrated Circuits Conference 1994 259 266 IEEE Custom Integrated Circuits Conference 1994 1994
2. D. Sylvester C. Hu O.S. Nakagawa S.-Y. Oh Interconnect scaling: signal integrity and performance in future high-speed CMOS designs 1998 Symposium on VLSI Technology, Digest of Technical Papers 1998 Symposium on VLSI Technology, Digest of Technical Papers 1998
3. A.B. Kahng S. Muddu E. Sarto R. Sharma Interconnect tuning strategies for high-performance ICs Design, Automation and Test in Europe 471 478 1998
4. Q.J. Zhang F. Wang M.S. Nakhla J.W. Bandler R.M. Biernacki Signal integrity optimization of high-speed VLSI packages and interconnects 48th IEEE Electronic Components and Technology Conference 1073 1076 48th IEEE Electronic Components and Technology Conference 1998
5. C. Visweswariah Optimization techniques for high-performance digital circuits 1997 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers 1997 IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers 1997
6. L. Gal On-chip cross talk-the new signal integrity challenge IEEE Custom Integrated Circuits Conference 1995 251 254 IEEE Custom Integrated Circuits Conference 1995 1995
7. J. M. Daga D. Auvergne A comprehensive delay macro modeling for submicrometer CMOS logics IEEE Journal of Solid-State Circuits 42 55 Jan 1999
8. D. Somasekhar Power and dynamic noise considerations in high performance CMOS VLSI 1999 Purdue University