Modular verification of time circuits using automatic abstraction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 9, 2003, Pages 1138-1153

  Zheng, Hao ^a   Mercer, Eric ^b   Myers, Chris ^c  

^a IBM   (United States)

^b 3361 TMCB   (United States)

^c University of Utah   (United States)

Author keywords

Abstraction; Modular verification; Timed circuits

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT;

AUTOMATIC ABSTRACTION; MODULAR VERIFICATION; TIMED CIRCUITS;

TIMING CIRCUITS;

EID: 0141740758     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.816214     Document Type: Article

References (48)

1. H. P. Hofstee, S. H. Dhong, D. Metzer, K. J. Nowka, J. A. Siblerman, J. L. Burns, S. D. Posluszny, and O. Takahashi, "Designing for a giga-hertz," IEEE MICRO, pp. 66-74, May-June 1998.
2. K. S. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken, "An asynchronous instruction length decoder," IEEE J. Solid-State Circuits, vol. 36, pp. 217-228, Feb. 2001.
3. D. Dill, Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. Cambridge, MA: MIT Press, 1989, ACM Distinguished Dissertations.
4. J. R. Burch, "Modeling timing assumptions with trace theory," in Proc. Int. Conf. Comput. Design, 1989, pp. 208-211.
5. J. Burch, "Delay models for verifying speed-dependent asynchronous circuits," in ACM Int. Workshop Timing Issues Specification Synthesis Digital Syst., Mar. 1992.
6. R. Alur and D. L. Dill, "A theory of timed automata," Theoretical Comput. Sci., vol. 126, no. 2, pp. 183-235, 1994.
7. D. Dill, S. Nowick, and R. Sproull, "Specification and Automatic Verification of Self-Timed Queues," Stanford Univ., Stanford, CA, Tech. Rep. CSL-TR-89-387, 1989.
8. W. Belluomini and C. J. Myers, "Timed state space exploration using posets," IEEE Trans. Computer-Aided Design, vol. 19, pp. 501-520, May 2000.
9. ____, "Timed circuit verification using tel structures," IEEE Trans. Computer-Aided Design, vol. 20, pp. 129-146, Jan. 2001.
10. C. Myers, W. Belluomini, K. Killpack, E. Mercer, E. Peskin, and H. Zheng, "Timed circuits: A new paradigm for high-speed design," in Proc. Asia South Pacific Design Automation Conf., Feb. 2001, pp. 335-340.
11. Y. Yoneda and H. Ryu, "Timed trace theoretic verification using partial order reduction," in Proc. Int. Symp. Adv. Res. Asynchronous Circuits Syst., Apr. 1999, pp. 108-121.
12. T. G. Rokicki "Representing and Modeling Circuits," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1993.
13. T. G. Rokicki and C. J. Myers, "Automatic verification of timed circuits," in Proc. Int. Conf. Computer-Aided Verification, 1994, pp. 468-480.
14. S. Yovine, "KRONOS: A verification tool for real-time systems," Springer Int. J. Software Tools Technol. Transfer, vol. 1, no. 1/s2, Oct. 1997.
15. J. Bengtsson, K. G. Larsen, F. Larsson, P. Pettersson, and W. Yi, "UPPAAL - A tool suite for automatic verification of real-time systems," in Hybrid Syst., 1995, vol. 1066, LNCS, pp. 232-243.
16. 20 states and beyond," Inform. Computat., vol. 98, no. 2, pp. 142-170, 1998.
17. K. McMillan, "Symbolic Model Checking: An Approach to the State Explosion Problem," Ph.D. dissertation, Carnegie Mellon Univ., Pittsburgh, PA, 1993.
18. R. E. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 677-691, Aug. 1986.
19. M. Bozga, O. Maler, A. Pnueli, and S. Yovine, "Some progress in the symbolic verification of timed automata," in Int. Conf. Computer-Aided Verification, vol. 1254, LNCS, 1997.
20. R. A. Thacker, W. Belluomini, and C. J. Myers, "Timed circuit synthesis using implicit methods," in Proc. Int. Conf. VLSI Design, 1999, pp. 181-188.
21. A. Valmari, "A stubborn attack on state explosion," in Proc. Int. Conf. Computer-Aided Verification, vol. 531, LNCS, June 1990, pp. 176-185.
22. P. Godefroid, "Using partial orders to improve automatic verification methods," in Proc. Int. Conf. Computer-Aided Verification, vol. 531, LNCS, 1990, pp. 176-185.
23. K. McMillan, "Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits," in Proc. Int. Workshop Computer-Aided Verification, vol. 663, LNCS, G. v. Bochman and D. K. Porbst, Eds., 1992, pp. 164-177.
24. J. Bengtsson, B. Jonsson, J. Lilius, and W. Yi, "Partial order reductions for timed systems," in Proc. Int. Conf. Concurrency Theory, 1998, pp. 485-500.
25. O. Grumberg and D. Long, "Model checking and modular verification," ACM Trans. Programm. Lang. Syst., vol. 16, pp. 843-872, 1994.
26. S. Tasiran, R. Alur, R. Kurshan and R. Brayton, "Verifying abstractions of timed systems," in Proc. 7th Int. Conf. Concurrency Theory, vol. 1119, LNCS, 1996, pp. 546-562.
27. S. Tasiran and R. K. Brayton, "Stari: A case study in compositional and heirarchical timing verification," in Proc. Int. Conf. Computer-Aided Verification, vol. 1254, LNCS, 1997.
28. E. Clarke, O. Grumberg, and D. Long, "Model checking and abstraction," ACM Trans. Programm. Lang. Syst., vol. 16, no. 5, pp. 1512-1542, 1994.
29. D. Dams, R. Gerth, and O. Grumberg, "Abstract interpretation of reactive systems," ACM Trans. Programm. Lang. Syst., vol. 19, no. 2, pp. 253-291, 1997.
30. C. Ramchandani, "Analysis of Asynchronous Concurrent Systems by Timed Petri Nets," Mass. Inst. Technol., Cambridge, MA, Tech. Rep. Project MAC Tech. Rep. 120, 1974.
31. M. R. Greenstreet, Stari: Skew Tolerant Communication, 1997.
32. C. A. R. Hoare, Communicating Sequential Processes. Englewood Cliffs, NJ: Prentice-Hall, 1985.
33. R. Milner, Communication and Concurrency. Englewood Cliffs, NJ: Prentice-Hall, 1989.
34. J. Snepscheut, Trace Theory and VLSI Design. New York: Springer-Verlag, 1985, vol. 200, LNCS.
35. J. R. Burch, "Trace Algebra for Automatic Verification of Real-Time Concurrent Systems," Ph.D. dissertation, Carnegie Mellon Univ., Pittsburgh, PA, 1992.
36. D. Dill, Private Communications. Stanford, CA: Stanford Univ., 2000.
37. I. Suzuki and T. Murata, Stepwise Refinements for Transitions and Places. New York: Springer-Verlag, 1982.
38. ____, "A method for stepwise refinements and abstractions of petri nets," J. Comput. Syst. Sci., vol. 27, no. 1, pp. 51-76, 1983.
39. G. Berthelot, Checking Properties of Nets Using Transformations. LNCS, 1986, vol. 222, New York: Springer-Verlag, pp. 19-40.
40. R. Johnsonbaugh and T. Murata, "Additional methods for reduction and expansion of marked graphs," IEEE Trans. Circuits Syst., vol. CAS-28, pp. 1009-1014, Oct. 1981.
41. T. Murata, "Petri nets: Properties, analysis, and applications," Proc. IEEE, vol. 77, pp. 541-580, Apr. 1989.
42. T. Murata and J. Y. Koh, "Reduction and expansion of live and safe marked graphs," IEEE Trans. Circuits Syst., vol. CAS-27, pp. 68-70, Jan. 1980.
43. H. Zheng, "Automatic Abstraction for Synthesis and Verification of Timed Systems," Ph.D. dissertation, Univ. Utah, Salt Lake City, 2001.
44. ____, "Specification and Compilation of Timed Systems," master's thesis, Univ. Utah, Salt Lake City, 1998.
45. E. Mercer, C. Myers, and T. Yoneda, "Improved poset timing analysis in timed petri nets," in Proc. 10th Workshop Synthesis Syst. Integration Mixed Technol., Oct. 2001.
46. C. Molnar, I. Jones, B. Coates, and J. Leaux, "A FIFO ring oscillator performance experiment," in Proc. Int. Symp. Adv. Res. Asynchronous Circuits Syst., Apr. 1997, pp. 279-289.
47. R. Alur and R. P. Kurshan, "Timing analysis in cospan," in Hybrid Syst. III: Verification and Control. New York: Springer-Verlag, vol. 1066, LNCS, pp. 220-231.
48. M. Bozga, O. Maler, and S. Tripakis, "Modeling and verification of the stari chip using timed automata," in Proc. 10th IFIP WG10.5 Adv. Res. Working Conf. Correct Hardware Design Verification Methods, 1703, 1999, pp. 125-141.