Timed circuit verification using TEL structures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 1, 2001, Pages 129-146

  Belluomini, Wendy ^a,b   Myers, Chris J ^a,c   Peter Hofstee, H ^a,b  

^a IEEE   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c University of Utah   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TIMED EVENT/LEVEL (TEL) STRUCTURES;

ALGORITHMS; COMPUTER SIMULATION; FINITE AUTOMATA; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS;

TIMING CIRCUITS;

EID: 0035057269     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.905681     Document Type: Article

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