Timed circuits: A new paradigm for high-speed design

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 335-340

  Myers, C J ^a   Belluomini, W ^a   Killpack, K ^a   Mercer, E ^a   Peskin, E ^a   Zheng, Hao ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Asynchronous circuits; Books; Circuit synthesis; Cities and towns; Contracts; Decoding; Delay; Engineering profession; Microprocessors; Timing

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER AIDED DESIGN; CONTRACTS; DECODING; DELAY CIRCUITS; DESIGN; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PROFESSIONAL ASPECTS;

ASYNCHRONOUS CIRCUITS; BOOKS; CIRCUIT SYNTHESIS; CITIES AND TOWNS; DELAY; ENGINEERING PROFESSION; TIMING;

TIMING CIRCUITS;

EID: 84949797246     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913329     Document Type: Conference Paper

References (13)

1. W. Belluomini and C. J. Myers. Timed state space exploration using posets. IEEE Transactions on Computer-Aided-Design, May 2000.
2. W. Belluomini, C. J. Myers, and H. P. Hofstee. Verification of delayed-reset domino circuits using ATACS. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 3-12, April 1999.
3. W. Belluomini and C.J. Myers. Verification of timed systems using posets. In International Conference on Computer Aided Verification. Springer-Verlag, 1998.
4. R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem. Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes. Patent granted September 7, 1999, patent number 5,948,096.
5. R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem. Branch instruction handling in a self-timed marking system. Patent granted August 3, 1999, patent number 5,931,944.
6. R. Ginosar, R. Kol, K. Stevens, P. Beerel, K. Yun, C. Myers, and S. Rotem. Efficient self-timed marking of lengthy variable length instructions. Patent granted August 24, 1999, patent number 5,941,982.
7. H. P. Hofstee, S. H. Dhong, D. Meltzer, K. J. Nowka, J. A. Silberman, J. L. Burns, S. D. Posluszny, and O. Takahashi. Designing for a gigahertz. IEEE MICRO, May-June 1998.
8. K. C. Killpack, E. Mercer, and C. J. Myers. A standard-cell self-timed multiplier for power and area critical synchronous systems. In Advanced Research in VLSI. CS Press, 2001.
9. C. J. Myers. Asynchronous Circuit Design. Wiley, New York, 2001.
10. C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.
11. T. G. Rokicki and C. J. Myers. Automatic verificaton of timed circuits. In International Conference on Computer-Aided Verification, pages 468-480. Springer-Verlag, 1994.
12. Shai Rotem, Ken Stevens, Ran Ginosar, Peter Beerel, Chris Myers, Kenneth Yun, Rakefet Kol, Charles Dike, Marly Roncken, and Boris Agapiev. RAPPID: An asynchronous instruction length decoder. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 60-70, April 1999.
13. H. Zheng and C. J. Myers. Automatic abstraction for synthesis and verification of deterministic timed systems. In collection of papers from TAU'00.