Timed trace theoretic verification using partial order reduction

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 1999, Pages 108-121

  Yoneda, Tomohiro ^a   Ryu, Hiroshi ^b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

PARTIAL ORDER REDUCTIONS; TIMED CIRCUITS; TRACE THEORETIC VERIFICATION;

EID: 77957933799     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1999.761527     Document Type: Conference Paper

References (18)

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