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Volumn 818 LNCS, Issue , 1994, Pages 468-480

Automatic verification of timed circuits

Author keywords

[No Author keywords available]

Indexed keywords

SEMANTICS; TIMING CIRCUITS;

EID: 85027193321     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-58179-0_76     Document Type: Conference Paper
Times cited : (36)

References (19)
  • 1
    • 0027617937 scopus 로고
    • Synthesis of timed asynchronous circuits
    • June
    • Chris J. Myers and Teresa H.-Y. Meng. Synthesis of timed asynchronous circuits. 1EEE Transactions on VLSI Systems, 1(2):106-119, June 1993.
    • (1993) 1EEE Transactions on VLSI Systems , vol.1 , Issue.2 , pp. 106-119
    • Myers, C.J.1    Meng, T.H.-Y.2
  • 2
    • 11744385419 scopus 로고
    • Programming in VLSI: From communicating processes to delay-insensitive VLSI circuits
    • In C.A.R. Hoare, editor, Addison-Wesley
    • Alain J. Martin. Programming in VLSI: From communicating processes to delay-insensitive VLSI circuits. In C.A.R. Hoare, editor, UT Year of Programming Institute on Concurrent Programming. Addison-Wesley, 1990.
    • (1990) UT Year of Programming Institute on Concurrent Programming
    • Martin, A.J.1
  • 3
    • 0020500372 scopus 로고
    • Trace theory and the definition of hierarchical components
    • In R. Bryant, editor, Computer Science Press, Inc
    • Martin Rem, Jan L. A. van de Snepscheut, and Jan Tijmen Udding. Trace theory and the definition of hierarchical components. In R. Bryant, editor, Third Caltech Conference on VLSI, pages 225-239. Computer Science Press, Inc., 1983.
    • (1983) Third Caltech Conference on VLSI , pp. 225-239
    • Rem, M.1    Van de Snepscheut, J.L.A.2    Udding, J.T.3
  • 4
    • 0003889387 scopus 로고
    • Trace theory for automatic hierarchial verification of speed-independent circuits
    • David L. Dill. Trace theory for automatic hierarchial verification of speed-independent circuits. ACM Distinguished Dissertations, 1989.
    • (1989) ACM Distinguished Dissertations
    • Dill, D.L.1
  • 8
    • 0026120365 scopus 로고
    • Modeling and verification of time dependent systems using time petri nets
    • March
    • Bernard Berthomieu and Michel Diaz. Modeling and verification of time dependent systems using time petri nets. IEEE Transactions on Software Engineering, 17(3), March 1991.
    • (1991) IEEE Transactions on Software Engineering , vol.17 , Issue.3
    • Berthomieu, B.1    Diaz, M.2
  • 9
  • 11
    • 84947978347 scopus 로고
    • Delay analysis in synchronous programs
    • In Costas Courcoubetis, editor, Springer-Vedag
    • Nicolas Halbwachs. Delay analysis in synchronous programs. In Costas Courcoubetis, editor, Computer Aided Verification, pages 333-346. Springer-Vedag, 1993.
    • (1993) Computer Aided Verification , pp. 333-346
    • Halbwachs, N.1
  • 12
    • 84957699348 scopus 로고
    • Efficient verification of parallel real-time systems
    • In Costas Courcoubetis, editor, Springer-Vedag
    • Tomohiro Yoneda, Atsufumi Shibayama, Bemd-Hologer Schlingloff, and Edmund M. Clarke. Efficient verification of parallel real-time systems. In Costas Courcoubetis, editor, Computer Aided Verification, pages 321-332. Springer-Vedag, 1993.
    • (1993) Computer Aided Verification , pp. 321-332
    • Yoneda, T.1    Shibayama, A.2    Schlingloff, B.-H.3    Clarke, E.M.4
  • 14
    • 0026926253 scopus 로고
    • Semi-modularity and testability of speedindependent circuits
    • September
    • Peter A. Beerel and Teresa H.-Y. Meng. Semi-modularity and testability of speedindependent circuits. INTEGRATION, the VLSljournal, 13(3):301-322, September 1992.
    • (1992) INTEGRATION, the VLSljournal , vol.13 , Issue.3 , pp. 301-322
    • Beerel, P.A.1    Meng, T.H.-Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.