A new accurate yield prediction method for system-LSI embedded memories

IEEE Transactions on Semiconductor Manufacturing

Volumn 16, Issue 3, 2003, Pages 436-445

  Shimada, Yutaka ^a   Sakurai, Koichi ^a  

^a IEEE   (Japan)

Author keywords

Embedded memory; Failure; Redundancy; Semiconductor manufacturing; Yield prediction

Indexed keywords

BIT ERROR RATE; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; NUMERICAL ANALYSIS; REDUNDANCY; SEMICONDUCTOR DEVICE MANUFACTURE;

COLUMN REDUNDANCY SETS; EMBEDDED MEMORY; YIELD PREDICTION;

LSI CIRCUITS;

EID: 0042386772     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2003.815636     Document Type: Article

References (21)

1. A. Shubat, "Moving the market to embedded memory," IEEE Design Test Comput., vol. 18, pp. 5-6, May-June 2001.
2. C. H. Stapper, "Defect density distributions for LSI yield calculations," IEEE Trans. Electron Devices, vol. ED-20, pp. 655-657, July 1973.
3. A. V. Ferris-Prabhu, "Role of defect size distribution in yield modeling," IEEE Trans. Electron Devices, vol. ED-32, pp. 1727-1736, Sept. 1985.
4. J. A. Cunnigham, "The use and evaluation of yield models in integrated circuit manufacturing," IEEE Trans. Semiconduct. Manufact., vol. 3, pp. 60-71, May 1990.
5. R. Glang, "Defect size distribution in VLSI chips," IEEE Trans. Semiconduct. Manufact., vol. 4, pp. 265-269, Nov. 1991.
6. C. N. Berglund, "A unified yield model incorporating both defect and parametric effects," IEEE Trans. Semiconduct. Manufact., vol. 9, pp. 447-454, Aug. 1996.
7. K. Sakurai, Y. Shimada, and K. Yamanishi, "A defect-situation forecasting technology to optimize future DRAM-redundancy design," in Int. Symp. Semiconductor Manufacturing Proc. (ISSM), 1997, pp. E43-E46.
8. H. Sato, M. Ikota, A. Sugimoto, and H. Masuda, "A new defect distribution metrology with a consistent discrete exponential formula and its applications," IEEE Trans. Semiconduct. Manuf., vol. 12, pp. 409-418, Nov. 1999.
9. C. Hess, D. Stashower, B. E. Stine, L. H. Weiland, G. Verma, K. Miyamato, and K. Inoue, "Fast extraction of defect size distribution using a single layer short flow NEST structure," IEEE Trans. Semiconduct. Manufact., vol. 14, pp. 330-337, Nov. 2001.
10. J. Khare, D. B. I. Feltham, and W. Maly, "Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits," IEEE J. Solid-State Circuits, vol. 28, pp. 146-156, Feb. 1993.
11. I. Koren and Z. Koren, "Defect tolerance in VLSI circuits: Techniques and yield analysis," Proc. IEEE, vol. 86, pp. 1819-1838, Sept. 1998.
12. K. Mitsutake and Y. Ushiku, "Yield model with redundancy based on critical area calculations," in Int. Symp. Semiconductor Manufacturing Proc. (ISSM), 2000, pp. 187-190.
13. C. H. Stapper, A. N. McLaren, and M. Dreckmann, "Yield model for productivity optimization of VLSI memory chips with redundancy and partially good product," IBM J. Res. Develop., vol. 24, no. 3, pp. 398-409, May 1980.
14. S. Kikuda, H. Miyamoto, S. Mori, M. Niiro, and M. Yamada, "Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond," IEEE J. Solid-State Circuits, vol. 26, pp. 1550-1555, Nov. 1991.
15. C. H. Stapper, "Improved yield models for fault-tolerant memory chips," IEEE Trans. Comput., vol. 42, pp. 872-881, July 1993.
16. J. R. Day, "A fault-driven, comprehensive redundancy algorithm," IEEE Design Test Comput., vol. 2, pp. 35-44, June 1985.
17. T. Sugibayashi, I. Naritake, S. Utsugi, K. Shibahara, R. Oikawa, H. Mori, S. Iwao, T. Murotani, K. Koyama, S. Fukuzawa, T. Itani, K. Kasama, T. Okuda, S. Ohya, and M. Ogawa, "A 1-Gb DRAM for file applications," IEEE J. Solid-State Circuits, vol. 30, pp. 1277-1280, Nov. 1995.
18. T. Yamagata, H. Sato, K. Fujita, Y. Nishimura, and K. Anami, "A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond," IEEE J. Solid-State Circuits, vol. 31, pp. 195-201, Feb. 1996.
19. T. Kirihata, Y. Watanabe, H. Wong, J. K. DeBrosse, M. Yoshida, D. Kato, S. Fujii, M. R. Wordeman, P. Poechmuller, S. A. Parke, and Y. Asao, "Fault-tolerant designs for 256 Mb DRAM," IEEE J. Solid-State Circuits, vol. 31, pp. 558-566, Apr. 1996.
20. I. Koren and Z. Koren, "Yield analysis of a novel scheme for defect-tolerant memories," in Proc. 1996 IEEE Int. Conf. Innovative System in Silicon, Austin, TX, Oct. 1996, pp. 269-278.
21. J. H. Yoo, C. H. Kim, K. C. Lee, K. H. Kyung, S. M. Yoo, J. H. Lee, M. H. Son, J. M. Han, B. M. Kang, E. Haq, S. B. Lee, J. H. Sim, J. H. Kim, B. S. Moon, K. Y. Kim, J. G. Park, K. P. Lee, K. N. Kim, S. I. Cho, J. P. Park, and H. K. Lim, "A 32-bank 1 Gb self-strobing synchronous DRAM with 1 Gbyte/s bandwidth," IEEE J. Solid-State Circuits, vol. 31, pp. 1635-1644, Nov. 1996.