Defect-situation forecasting technology to optimize future DRAM-redundancy design

IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 1997, Pages

  Sakurai, Koichi ^a   Shimada, Yutaka ^a   Yamanishi, Ken ichiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL DEFECTS; OPTIMIZATION; RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS MEMORY (DRAM);

INTEGRATED CIRCUIT LAYOUT;

EID: 0031348039     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)