Fast extraction of defect size distribution using a single layer short flow NEST structure

IEEE Transactions on Semiconductor Manufacturing

Volumn 14, Issue 4, 2001, Pages 330-337

  Hess, Christopher ^a,b   Stashower, David ^b   Stine, Brian E ^b   Weiland, Larg H ^a,b   Verma, Gaurav ^c   Miyamoto, Koji ^d   Inoue, Kotaro ^d  

^a IEEE   (United States)

^b PDF SOLUTIONS INC   (United States)

^c KLA TENCOR CORPORATION   (United States)

^d TOSHIBA CORPORATION   (Japan)

Author keywords

Semiconductor devices; Test structures; Yield estimation; Yield optimization

Indexed keywords

DATA EXTRACTION; DEFECT INSPECTION; DEFECT SIZE DISTRIBUTION;

DATA REDUCTION; DEFECTS; ELECTRIC VARIABLES MEASUREMENT; FAILURE ANALYSIS; OPTIMIZATION; PROCESS CONTROL; QUALITY CONTROL; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035508752     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.964320     Document Type: Article

References (5)

1. Defect size-distribution in VLSI chips
2. A digital tester based measurement methodology for process control in multilevel metallization systems
3. Harp test structure to electrically determine size distributions of killer defects
4. Extraction of defect size distributions in an IC layer using test structure data
5. Integrated circuit yield management and yield analysis: Development and implementation