Yield analysis of a novel scheme for defect-tolerant memories

Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon

Volumn , Issue , 1996, Pages 269-278

  Koren, Israel ^a   Koran, Zahava ^a  

^a UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; STORAGE ALLOCATION (COMPUTER);

FLEXIBLE MULTI MACRO (FMM) TECHNIQUE; MEMORY INTEGRATED CIRCUIT DEFECT TOLERANCE;

RANDOM ACCESS STORAGE;

EID: 0030397732     PISSN: 10632204     EISSN: None     Source Type: None    
DOI: 10.1109/ICISS.1996.552434     Document Type: Conference Paper

References (6)

1. G. Kitsukawa 256-Mb DRAM Circuit Technologies for File Applications IEEE J. of Solid-State Circuits 28 1105 11101 Nov. 1993
2. I. Koren Z. Koren C. H. Stapper A Unified Negative Binomial Distribution for Yield Analysis of Defect Tolerant Circuits IEEE Trans. on Computers 42 724 437 June 1993
3. I. Koren C. H. Stapper Defect and Fault Tolerance in VLSI Systems 1 21 1989 Plenum Yield Models for Defect Tolerant VLSI Circuit: A Review
4. T. Sugibayashi A 1-Gb DRAM for File Applications IEEE J. of Solid-State Circuits 30 1277 1280 Nov. 1995
5. T. Yamagata A Distributed Globally Replaceable Redundancy Scheme for Sub-Half-micron ULSI Memories and Beyond IEEE J. of Solid-State Circuits 31 195 201 Feb. 1996
6. J-H. Yoo A 32-Bank 1Gb DRAM with 1GB/s Bandwidth ISSSC Dig. Tech. Papers ISSSC Dig. Tech. Papers 1996-Feb.