A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1635-1642

  Yoo, Jei Hwan ^b,c   Kim, Chang Hyun ^a,b,d,e   Lee, Kyu Chan ^b,f   Kyung, Kye Hyun ^a,b,d   Yoo, Seung Moon ^b,g,h   Lee, Jung Hwa ^b   Son, Moon Hae ^b   Han, Jin Man ^b   Kang, Bok Moon ^b   Haq, Ejaz ^b   Lee, Sang Bo ^b   Sim, Jai Hoon ^a,b   Kim, Joung Ho ^b   Moon, Byung Sik ^b   Kim, Keum Yong ^b   Park, Jae Gwan ^b   Lee, Kyu Phil ^b   Lee, Kang Yoon ^b   Kim, Ki Nam ^b   Cho, Soo In ^b   Park, Jong Woo ^a,b   Lim, Hyung Kyu ^a,b   more..

^a IEEE

^b SAMSUNG Electronics   (South Korea)

^c Yonsei University   (South Korea)

^d Seoul National University   (South Korea)

^e UNIVERSITY OF MICHIGAN   (United States)

^f Chung Ang University   (South Korea)

^g Kyungpook National University   (South Korea)

^h UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; SEMICONDUCTOR STORAGE;

BLOCK REDUNDANCY SCHEME; MULTIBANK ARCHITECTURE; SELF STROBING SCHEMES;

RANDOM ACCESS STORAGE;

EID: 0030287774     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542308     Document Type: Article

References (9)

1. N. Kushiyama et al., "A 500 Mbyte/s data-rate 4.5 M DRAM," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 490-498, Apr. 1993.
2. H. J. Yoo et at., "A 150 MHz 8-banks 256 M synchronous DRAM with wave pipelining methods," in ISSCC Dig. Tech. Papers, Feb. 1995, pp. 250-251.
3. S. Tanoi et al., "A 32-bank 256 Mb DRAM with cache and TAG," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 144-145.
4. H. J. Yoo et al., "A 150 MHz 8-banks 256 M synchronous DRAM with wave pipelining methods," in ISSCC Slide Supplement to the Dig. Tech. Papers. Feb. 1995, pp. 186-187.
5. H. T. Lee et al., "A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM," IEEE J. Solid-State Circuits, pp. 1491-1496, vol. 29, no. 12, Dec. 1994.
6. M. Asakura et al., "A 34 ns 256 Mb DRAM with boosted sense-grounded scheme," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 140-141.
7. G. Kitsukawa et al., "256 Mb DRAM technologies for file applications," in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 48-49.
8. T. Kirihara et al., "Fault-tolerant designs for 256 Mb DRAM," in Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 107-108.
9. K. P. Lee et al., "A process technology for 1 Gbit DRAM," in IEDM Dig. Tech. Papers, Dec. 1995, pp. 907-910.