A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

IEEE Transactions on Electron Devices

Volumn 50, Issue 9, 2003, Pages 1952-1960

  Zhang, Shengdong ^a   Chan, Alain Chun Keung ^b   Han, Ruqi ^a   Huang, Ru ^a   Liu, Xiaoyan ^a   Wang, Yangyuan ^a   Ko, Ping K ^b   Chan, Mansun ^b  

^a PEKING UNIVERSITY   (China)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Bottom gate; MOSFET; Self aligned structure; SRAM

Indexed keywords

COMPUTER SIMULATION; CRYSTALLIZATION; GATES (TRANSISTOR); POLYSILICON; RECRYSTALLIZATION (METALLURGY); STATIC RANDOM ACCESS STORAGE;

DEVICE SIMULATOR; SOLID PHASE CRYSTALLIZATION; THERMAL OXIDE;

MOSFET DEVICES;

EID: 0041910811     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.815859     Document Type: Article

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