Implementation of fully self-aligned bottom-gate MOS transistor

IEEE Electron Device Letters

Volumn 23, Issue 10, 2002, Pages 618-620

  Zhang, Shengdong ^c   Han, Ruqi ^c   Zhang, Zhikuan ^a,b   Huang, Ru ^c   Ko, Ping K ^a,b   Chan, Mansun ^a,b  

^a IEEE

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c PEKING UNIVERSITY   (China)

Author keywords

Bottom gate; Low pressure chemical vapor deposition (LPCVD); MOSFET; Self aligned structure; Static random access memory (SRAM)

Indexed keywords

ANNEALING; CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; GATES (TRANSISTOR); ION IMPLANTATION; POLYSILICON; SEMICONDUCTING FILMS; SEMICONDUCTOR DOPING; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

CHEMOMECHANICAL POLISH; LIGHTLY DOPED DRAIN; LOW PRESSURE CHEMICAL VAPOR DEPOSITION; POLYSILICON FILM;

MOSFET DEVICES;

EID: 0036803381     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2002.803763     Document Type: Article

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