RF CMOS on high-resistivity substrates for system-on-chip applications

IEEE Transactions on Electron Devices

Volumn 50, Issue 3, 2003, Pages 567-576

  Benaissa, Kamel ^a   Yang, Jau Yuann ^a   Crenshaw, Darius ^a   Williams, Byron ^a   Sridhar, Seetharaman ^a   Ai, Johnny ^a   Boselli, Gianluca ^a   Zhao, Song ^a   Tang, Shaoping ^a   Ashburn, Stanton ^a   Madhani, Praful ^a   Blythe, Timothy ^a   Mahalingam, Nandu ^a   Shichijo, Hisashi Sam ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COPPER; ELECTRIC CONDUCTIVITY; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE STRUCTURES; SILICON WAFERS; SPURIOUS SIGNAL NOISE; SUBSTRATES; THRESHOLD VOLTAGE;

COPPER METAL PITCH; GUARD RING STRUCTURE; SUBSTRATE COUPLING; SYSTEM-ON-A-CHIP;

CMOS INTEGRATED CIRCUITS;

EID: 0038714252     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.810470     Document Type: Article

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