Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 2152-2155

  Li, Yiming ^a,b   Lee, Jam Wem ^a   Sze, Simon M ^a,b  

^a NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

2D HD simulation; Anti punch through implant; Electron temperature; ESD protection device

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CURRENT DENSITY; ELECTRIC DISCHARGES; ELECTROSTATICS; HYDRODYNAMICS; MODELS; OPTIMIZATION; TEMPERATURE; THERMAL INSULATING MATERIALS; TWO DIMENSIONAL;

ANTI PUNCH THROUGH IMPLANT; ELECTRON TEMPERATURE; ELECTROSTATIC DISCHARGE PROTECTION DEVICE; TWO DIMENSIONAL HYDRODYNAMIC COMPUTER SIMULATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038686438     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.42.2152     Document Type: Article

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