Analysis and design of ESD protection circuits for high-frequency/RF applications

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 117-122

  Ito, Choshu ^a   Banerjee, Kaustav ^a   Dutton, Robert W ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COPLANAR WAVEGUIDES; DESIGN; ELECTROSTATIC DISCHARGE; IMPEDANCE MATCHING (ELECTRIC); SCATTERING PARAMETERS;

BROAD FREQUENCY RANGE; DESIGN METHODOLOGY; ELECTROSTATIC DISCHARGE PROTECTION DEVICE (ESD); ESD PROTECTION; ESD PROTECTION CIRCUIT; HIGH FREQUENCY HF; IMPEDANCE MATCH; PARASITIC CAPACITANCE;

ELECTROSTATIC DEVICES;

EID: 84949998095     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915215     Document Type: Conference Paper

References (8)

1. A. Amerasekera, "RF Protection Circuit Design Approaches," Tutorial Notes, EOS/ESD Symposium, 1999.
2. S. H. Voldman, "The State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation, and Scaling," IEEE J. of Solid-State Circuits, Vol. 34, No. 9, pp. 1272-1282, 1999.
3. A. Amerasekera, "ESD in Silicon Integrated Circuits," Wiley, NY, 1995.
4. K. Bock, "ESD Issues in Compound Semiconductor High Frequency Devices and Circuits," Proc. EOS/ESD Symp. 1997, pp. 1-12.
5. B. Kleveland, and T. Lee, US Patent # 5,929,969, Oct. 1999.
6. B. Kleveland, et al, "Distributed ESD Protection for High Speed Integrated Circuits," IEEE Electron Device Lett., Vol. 21, No. 8, pp. 390-392, 2000.
7. C. Richier, et al, "Investigation on Different ESD Protection Strategies Devoted to 3.3V RF Applications (2GHz) in a 0.18um CMOS Process," Proc. EOS/ESD Symp., 2000, pp. 251-259.
8. B. Kleveland, et al, "50GHz Interconnect Design in Standard Silicon Technology," Proc. MTT-S, 1998, pp. 1913-1916.