Test structure design considerations for RF-CV measurements on leakv dielectrics

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2003, Pages 181-185

  Schmitz, J ^a   Cubaynest, F N ^b   Havens, R J ^b   De Kort, R ^b   Scholten, A J ^b   Tiemeijer, L F ^b  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CURRENT DENSITY; GATES (TRANSISTOR); LEAKAGE CURRENTS; LOGIC DESIGN; VOLTAGE MEASUREMENT;

TEST STRUCTURES;

CMOS INTEGRATED CIRCUITS;

EID: 0038303539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors", VLSI Symp. Tech. Dig., pp. 174-175, 2000.
2. P. Masson, J.-L. Autran, and J. Brini, "On the tunneling component of charge pumping current in ultrathin gate oxide MOSFET's", IEEE Electron Device Lett., Vol. 20, no. 2, pp. 92-94, 1999.
3. J. Schmitz, H. P. Tuinhout, H. J. Kretschmann, and P. H. Woerlee, "Comparison of Soft-Breakdown Triggers for Large Area Capacitors", Transactions on Device and Materials Reliability, Vol. 1, no. 3, pp. 150-157, 2001.
4. W. K. Henson, K. Z. Ahmed, E. M. Vogel, J. R. Hauser, J. J. Wortman, R. D. Venables, M. Xu, and D. Venables, "Estimating Oxide Thickness of Tunnel Oxides Down to 1.4 nm Using Conventional Capacitance-Voltage Measurements on MOS Capacitors", IEEE Electron Device Lett., Vol. 20, no. 4, pp. 179-181, 1999.
5. J. Schmitz, "Capacitance-voltage measurements and gate leakage", Tutorial presented at the 2002 ICMTS Conference, Cork, Ireland.
6. C.-H. Choi, J.-S. Goo, T.-Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. Vande Voorde, D. Vook, and C. H. Diaz, "MOS C-V Characterization of Ultrathin Gate Oxide Thickness (1.3-1.8 nm)", IEEE Electron Device Lett., Vol. 20, no. 6, pp. 292-294, 1999.
7. K. J. Yang and C. Hu, "MOS Capacitance Measurements for High-Leakage Thin Dielectrics", IEEE Trans. Electron Devices, Vol. 46, no. 7, pp. 1500-1501, 1999.
8. D. W. Barlage, J. T. O'Keeffe, J. T. Kavalieros, M. M. Nguyen, and R. S. Chau, "Inversion MOS capacitance extraction for high-leakage dielectrics using a transmission line equivalent circuit", IEEE Electron Device Lett., Vol. 21, No. 9, pp. 454-456, 2000.
9. max realized at 0.18 μm gate length in an industrial RF-CMOS technology", IEDM Tech. Dig., 2001, pp. 223-226.
10. M. C. A. M. Koolen, J. A. M. Geelen, and M. P. J. G. Versleijen, "An improved de-embedding technique for on-wafer high frequency characterization", Proceedings BCTM, 1991, pp. 188-191.
11. L. F. Tiemeijer and D. B. M. Klaassen, "Geometry scaling of the substrate loss of RF MOSFETs", Proceedings of the ESSDERC 1998 Conference, pp.480-483.
12. J. Han, M. Je, and H. Shin, "A simple and accurate method for extracting substrate resistance of RF MOSFETs", IEEE Electron Device Lett., Vol. 23, no. 7, pp. 434-436, 2002.
13. Available: http://www.semiconductors.philips.com/Philips-models
14. D. W. Barlage, R. Arghavani, G. Dewey, M. Doczy, B. Doyle, J. T. Kavalieros, A. Murthy, B. Roberds, P. Stokley and R. S. Chau, "High-frequency response of 100nm integrated CMOS transistors with high-K gate dielectrics", IEDM Tech. Dig., 2001, pp. 231-234.