Geometry scaling of the substrate loss of RF MOSFETs

European Solid-State Device Research Conference

Volumn , Issue , 1998, Pages 480-483

  Tiemeijer, L F ^a   Klaassen, D B M ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

SCATTERING PARAMETERS;

GATE LENGTH; NMOS DEVICES; ON-WAFER; RF MOSFETS; SIGNAL S-PARAMETERS; SUBSTRATE LOSS;

MOS DEVICES;

EID: 84908209921     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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2. R. R. J. Vanoppen et al., "The high-frequency analogue performance of MOSFETs", Proceedings IEDM 1994, pp. 173-177.
3. R. R. J. Vanoppen et al., "RF Noise Modelling of 0. 25 p, m CMOS and low power LNAs" Proceedings IEDM 1997, pp. 317- 321.
4. W. Liu, "R. E MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model", Proceedings IEDM 1997, pp. 309-312.
5. M. A. C. Koolen et al., "An improved deembedding technique for on-wafer high frequency characterization", Proceedings BCTM 1991, pp. 188-191.
6. J. P. Tsividis, "Operation and Modeling of the MOS Transistor", McGraw-Hill, 1987.
7. S. M. Sze, "High Speed Semiconductor Devices", John Wiley, 1990.
8. S. P. Voinigescu et al., "an Assessment of the State-of-the-Art 0. 5 urn Bulk CMOS Technology for RF Applications", Proceedings IEDM 1995, pp. 721-724.
9. G. Gonzales, "Microwave Transistor Amplifiers", P rentice-Hall. Inc., 1984.