Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 749-752

  Ueki, M ^a   Hiroi, M ^a   Ikarashi, N ^a   Onodera, T ^a   Furutake, N ^a   Yoshiki, M ^a   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; MICROSTRUCTURE; PHYSICAL VAPOR DEPOSITION; STRESS ANALYSIS; TITANIUM;

VOID FORMATION;

ELECTROMIGRATION;

EID: 0036930468     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. E. T. Ogawa, et. al., IRPS 2002, p312 (2002).
2. N. Okada, et. al., 2002 IITC, p136 (2002).
3. T. Suzuki et. al., 2002 IITC, p229 (2002).
4. B. -L. Park, et. al., 2002 IITC, p130 (2002).
5. C. -K. Hu, et al., Applied Physios Letters, vol.74, p.2945 (1999).
6. S.P. Murarka, International Conference on Advanced Microelectronic Devices and Processing, P321 (1994).