Suppression of stress-induced voiding in copper interconnects

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2002, Pages 757-760

  Oshima, T ^a   Hinode, K ^a   Yamaguchi, H ^a   Aoki, H ^a   Torii K , ^a   Saito, T ^a   Ishikawa, K ^a   Noguchi, J ^a   Fukui, M ^a   Nakamura, T ^a   Uno, S ^a   Tsugane, K ^a   Murata, J ^a   Kikushima, K ^a   Sekisaka, H ^a   Murakami, E ^a   Okuyama, K ^a   Iwasaki, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADHESION; GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; OPTIMIZATION; STRESS CONCENTRATION; THERMAL DIFFUSION;

STRESS-INDUCED VOIDING (SIV);

COPPER;

EID: 0036927922     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. T. Oshima, T. Tamaru, K. Ohmori, H. Aoki, H. Ashihara, T. Saito, et al., "Improvement of thermal stability of via resistance in dual damascene copper interconnection," Proc. of IEDM, pp. 123-126 (2000).
2. E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, et al., "Stress-induced voiding under vias connected to wide Cu metal leads," Proc. of IRPS, pp, 312-321 (2002).
3. H. Aoki, K. Torii, T. Oshima, J. Noguchi, U. Tanaka, H. Yamaguchi, et al., "Robust 130nm-node Cu dual damascene technology with low-k barrier SiCN," Proc. of IEDM pp. 76-79 (2001).
4. T. Saito, T. Hashimoto, N. Ohashi, T. Fujiwara and H. Yamaguchi, "Copper wires for high speed logic LSI prepared by low pressure long through sputtering method," Materials Transactions, Vol.43, No.7 pp. 1599-1604 (2002)
5. K. Ishikawa, M. Miyauchi, H. Ashihara, T. Saitoh, S. Ishihara, T. Oshima, et al. resistance improvement of dual-damascene copper interconnection using Ta/TaN barrier formed by ionized bias sputtering," Proc. of Advanced Metallization Conference, p. 59 (2001).