Ultra-high-density interconnection technology of 3-dimensional packaging

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4931, Issue , 2002, Pages 354-359

  Takahashi, Kenji ^a   Umemoto, Mitsuo ^a   Tanida, Kazumasa ^a   Nemoto, Yoshihiko ^a   Tomita, Yoshihiro ^a   Tago, Masamoto ^a   Bonkohara, Manabu ^a  

^a ASSOCIATION OF SUPER ADVANCED ELECTRONICS TECHNOLOGIES ASET   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; COMPRESSION TESTING; COPPER; DIFFUSION; ELECTRON ENERGY LEVELS; FLIP CHIP DEVICES; INTERCONNECTION NETWORKS; INTERFACES (MATERIALS); RELIABILITY; SEMICONDUCTOR DEVICE TESTING; THERMAL CYCLING; ULTRASONIC APPLICATIONS;

ATOMIC LEVEL BONDING; BUMP BONDING; ELECTRICAL CONNECTION; TEMPERATURE CYCLING TEST; THERMO COMPRESSION BONDING; ULTRA HIGH DENSITY INTERCONNECTION TECHNOLOGY; ULTRASONIC FLIP-CHIP BONDING;

ELECTRONICS PACKAGING;

EID: 0036448518     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Kenji Takahashi, Hiroshi Terao, Yoshihiro Tomita, Yasuhiro Yamaji, Masataka Hoshino, Tomotoshi Sato, Tadahiro Morifuji, Masahiro Sunohara, Manabu Bonkohara, "Current Status of Research and Development for Three-Dimensional Chip Stack Technology," Jpn. J. Appl. Phys., Vol. 40, No. 4B p. 3032-3037, 2001.
2. Mitsuo Umemoto, Yoshihiro Tomita, Tadahiro Morifuji, Tatsuya Ando, Tomotoshi Sato and Kenji Takahashi, "Superfine Flip-Chip Interconnection in 20μm-Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI," Proc. 52nd Electron. Comp. Technol. Conf., pp. 1454-1495, 2002.
3. Kazumasa Tanida, Yoshihiro Tomita, Tadahiro Morifuji, Tatsuya Ando, Ryoichi Kajiwara, Naotaka Tanaka, Tomotoshi Sato, Kenji Takahashi and Manabu Bonkohara, "Superfine Flip Chip Interconnections in 20μm-pitch," 2002 Int. Conf. Electron. Packaging Proc., pp. 333-338, 2002.
4. Yoshihiro Tomita, Masamoto Tago, Yoshihiko Nemoto and Kenji Takahashi, "Cu Bump Interconnections in 20μm pitch utilizing Electroless Tin-Cap on 3D Stacked LSI," Adv. Electron. Mater. Packaging, pp. 107-114, 2001
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6. Masamoto Tago, Yoshihiro Tomita, Masahiro Sunohara, Tomonori Fujii, Tomotoshi Sato and Kenji Takahashi, Proc. 16th JIEP Ann. Meeting, pp. 307-308, 2002 [in Japanese].
7. Tadahiro Morifuji, Yoshihiro Tomita, Naotaka Tanaka, Tomotoshi Sato and Kenji Takahashi, "Flip-Chip Bonding Technologies utilizing Micro Au Bumps in 20μm-pitch," 8th Symp. Microjoining Assembly Technol. Electron., pp. 119-124, 2002 [in Japanese].
8. Tadatomo Suga and Kanji Otsuka, "Bump-Less Interconnections for Next Generation System Packaging," Proc. 51st Electron. Comp. Technol. Conf., pp. 1003-1008, 2001.
9. J. C. Fister and S. Paul Zarlingo, "Solderbility Performance of Tin Coated Copper Alloy Strip for Connector Components," Proc. 41st Electron. Comp. Technol. Conf., pp. 229-233, 1991.
10. Yoshihiro Tomita, Masamoto Tago, Yoshihiko Nemoto and Kenji Takahashi, "Copper Bump Bonding with Electroless Metal Cap on 3 Dimensional Stacked Structure," Proc. 3rd Electron. Packaging Technol. Conf., pp.286-291, 2000.