Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques

Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001

Volumn , Issue , 2001, Pages 71-77

  Chabini, N ^a   Aboulhamid, E M ^a   Savaria, Y ^b  

^a UNIVERSITÉ DE MONTRÉAL   (Canada)

^b ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CLOCKS; POLYNOMIAL APPROXIMATION; RECONFIGURABLE HARDWARE; SCHEDULING ALGORITHMS;

CLOCK GENERATION; CLOCK PERIOD; CLOCK PERIOD MINIMIZATION; CLOCKED CIRCUITS; POLYNOMIAL-TIME; SOFTWARE PIPELINING; SYNCHRONOUS CIRCUITS;

VLSI CIRCUITS;

EID: 84964547452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2001.923142     Document Type: Conference Paper

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