Evaluating integrated hardware-software optimizations using a unified energy estimation framework

IEEE Transactions on Computers

Volumn 52, Issue 1, 2003, Pages 59-76

  Vijaykrishnan, N ^a   Kandemir, Mahmut ^a   Irwin, Mary Jane ^a   Kim, Hyun Suk ^a   Ye, Wu ^b   Duarte, David ^a  

^a The Pennsylvania State University   (United States)

^b Applied Micro Circuits Corporation   (United States)

Author keywords

Energy estimation; Energy models; Optimizations; Simulation

Indexed keywords

CODES (SYMBOLS); DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; OPTIMIZATION; VIDEO SIGNAL PROCESSING;

ENERGY MODELS;

MICROPROCESSOR CHIPS;

EID: 0037249179     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1159754     Document Type: Article

References (42)

1. N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. Kim, and W. Ye, "Energy-Driven Integrated Hardware-Software Optimizations Using SimplePower," Proc. Int'l Symp. Computer Architecture, 2000.
2. D. Tennenhouse, Pro-Active Computing, http://www.darpa.mil/ito/Proceedings/DARPATech99.html, 1999.
3. A. Chandrakasan and R. Brodersen, Low Power Digital CMOS Design. Kluwer Academic, 1995.
4. D. Blaauw, A. Dharchoudhury, R. Panda, S. Sirichottiyakul, C. Oh, and T. Edwards, "Emerging Power Management Tools for Processor Design," Proc. Int'l Symp. Low Power Electronics and Design, pp. 143-148, Aug. 1998.
5. V. Tiwari, S. Malik, A. Wolfe, and T. Lee, "Instruction Level Power Analysis and Optimization of Software," J. VLSI Signal Processing Systems, vol. 13, no. 2, Aug. 1996.
6. Y. Li and J. Henkel, "A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems," Proc. Design Automation Conf., pp. 188-191, 1998.
7. D. Burger and T. Austin, "The Simplescalar Tool Set, Version 2.0," technical report, Computer Sciences Dept., Univ. of Wisconsin, June 1997.
8. F. Catthoor, S. Wuytack, E.D. Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle, Custom Memory Management Methodology-Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer Academic, June 1998.
9. P.R. Panda, N.D. Dutt, and A. Nicolau, "Architectural Exploration and Optimization of Local Memory in Embedded Systems," Proc. 10th Int'l Symp. System Synthesis, Sept. 1997.
10. K. Itoh, K. Sasaki, and Y. Nakagome, "Trends in Low-Power Ram Circuit Technologies," Proc. IEEE, vol. 83, no. 4, pp. 524-543, Apr. 1995.
11. C.L. Su and A.M. Despain, "Cache Designs for Energy Efficiency,' Proc. 28th Hawaii Int'l Conf. System Sciences, Jan. 1995.
12. K. Roy and M.C. Johnson, "Software Design for Low Power," NATO Advanced Study Inst. on Low Power Design in Deep Sub-Micron Electronics, Aug. 1996.
13. P. Song, "Embedded DRAM Finds Growing Niche," Microprocessor Report, pp. 19-23, Aug. 1997.
14. Y. Nunomura et al., "M32R/D-Integrating DRAM and Micro-processor," IEEE Micro, Nov./Dec. 1997.
15. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," Proc. 27th Int'l Symp. Computer Architecture, June 2000.
16. T. Simunic, L. Benini, and G.D. Micheli, "Cycle-Accurate Simulation of Energy Consumption in Embedded Systems," Proc. 36th ACM/IEEE Design Automation Conf., June 1999.
17. M. Kamble and K. Ghose, "Analytical Energy Dissipation Models for Low Power Caches," Proc. Int'l Symp. Low Power Electronics and Design, p. 143, Aug. 1997.
18. M.J. Irwin and N. Vijaykrishnan, "Energy Issues in Multimedia Systems," Proc. Workshop Signal Processing Systems, pp. 24-33, Oct. 1999.
19. R. Chen, N. Vijaykrishnan, and M.J. Irwin, "Clock Power Issues in System-on-Chip Designs," Proc. Ann. IEEE CS Workshop VLSL pp. 48-53, 1999.
20. D. Duarte, N. Vijaykrishnan, M.J. Irwin, and M. Kandemir, "Formulation and Validation of an Energy Dissipation Model for Clock Generation Circuitry and Distribution Network," Proc. 14th Int'l Conf. VLSI Design, Jan. 2001.
21. H. Mehta, R.M. Owens, and M.J. Irwin, "Energy Characterization Based on Clustering," Proc. 33rd Design Automation Conf., p. 702, June 1996.
22. META-SOFTWARE, "Star-Hspice User's Manual Version 96.1," Feb. 1996.
23. J. Lin, W. Shen, and J. Jou, "A Power Modeling and Characterization Method for Macrocells Using Structure Information," Proc. Int'l Conf. Computer Aided Design, p. 502, Nov. 1997.
24. R.Y. Chen, R.M. Owens, and M.J. Irwin, "Validation of an Architectural Level Power Analysis Technique," Proc. 35th Design Automation Conf., p. 242, June 1998.
25. W.-T. Shiue and C. Chakrabarti, "Memory Exploration for Low Power, Embedded Systems, clpe-tr-9-1999-20," technical report, Arizona State Univ., 1999.
26. D. Duarte, N. Vijaykrishnan, M.J. Irwin, and M. Kandemir, "Evaluating the Impact of Architectural-Level Optimizations on Clock Power," Proc. Int'l Conf. ASIC/SoC, Sept. 2001.
27. P. Hicks, M. Walnock, and R.M. Owens, "Analysis of Power Consumption in Memory Hierarchies," Proc. Int'l Symp. Low Power Electronics and Design, p. 239, 1997.
28. B. Ackland and C. Nicol, "High Performance DSPs-What's Hot and What's Not?" Proc. Int'l Symp. Low Power Electronics and Design, pp. 1-6, Aug. 1998.
29. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "Improving Locality Using Loop and Data Transformations in an Integrated Framework," Proc. 31st Int'l Symp. Microarchitecture, Dec. 1998.
30. M. Wolf, D. Maydan, and D. Chen, "Combining Loop Transformations Considering Caches and Scheduling," Proc. 29th Int'l Symp. Microarchitecture (MICRO-29), p. 274, Dec. 1996.
31. S. Carr and Y. Guan, "Unroll-and-Jam Using Uniformly Generated Sets," Proc. 30th Int'l Symp. Microarchitecture (MICRO-30), Dec. 1997.
32. S.S. Muchnick, Advanced Compiler Design Implementation. San Francisco: Morgan Kaufmann, 1997.
33. M. Wolfe, High Performance Compilers for Parallel Computing. Addison-Wesley, 1996.
34. S.Y. Liao, "Code Generation and Optimization for Embedded Digital Signal Processors," PhD thesis, Dept. of Electrical Eng. and Computer Science, Massachusetts Inst. of Technology, Cambridge, Mass., June 1996.
35. M. Chang, M. Irwin, and R. Owens, "Power-Area Trade-Offs in Divided Word Line Memory Arrays," J. Circuits, Systems, and Computers, vol. 7, no. 1, pp. 49-67, 1997.
36. J. Kin, G.M. Gupta, and W.H. Mangione-Smith, "The Filter Cache: An Energy Efficient Memory Structure," Proc. 30th Ann. Int'l Symp. Microarchitecture, pp. 184-193, 1997.
37. G. Albera and R.I. Bahar, "Power and Performance Tradeoffs Using Various Cache Configurations," Proc. Power Driven Micro-Architecture Workshop, Int'l Symp. Computer Architecture (ISCA '98), June 1998.
38. B. Calder, D. Grunwald, and J. Emer, "Predictive Sequential Associative Cache," Proc. Second Int'l Symp. High-Performance Computer Architecture, pp. 244-253, 1996.
39. K. Inoue, T. Ishihara, and K. Murakami, "Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption," Proc. Int'l Symp. Low Power Electronics and Design, pp. 273-275, 1999.
40. R.R. Kessler, R. Jooss, A. Lebeck, and M.D. Hill, "Inexpensive Implementations of Self-Associativity," Proc. 16th Ann. Int'l Symp. Computer Architecture, SIGARCH Newsletter, 1989.
41. M. Ohnishi, A. Yamada, H. Noda, and T. Kambe, "A Method of Redundant Clocking Detection and Power Reduction at RT Level Design," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED '97), p. 131, Aug. 1997.
42. T. Lang, E. Musol, and J. Cortadella, "Individual Flip-Flops with Gated Clocks for Low Power Datapaths," IEEE Trans. Circuits and System-II: Analog and Digital Signal Processing, vol. 44, no. 6, June 1997.