Evaluating the impact of architectural-level optimizations on clock power

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 447-451

  Duarte, D ^a   Narayanan, V ^a   Irwin, M J ^a   Kandemir, M ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

CLOCK ENERGY; CLOCK GATING; SYSTEM ON A CHIP;

TIMING CIRCUITS;

EID: 0034770993     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. Clock power issues in SoC designs
2. Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks
3. Clock distribution design in VLSI circuits: An overview
4. Energy-efficiency of VLSI caches: A comparative study
5. Simultaneous clock scheduling and buffered clock tree synthesis
6. A noise-immune GHz-clock distribution scheme using synchronous distributed oscillators
7. Designing the best clock distribution network
8. Designing the low-power MCORE architecture
9. High performance compilers for parallel computing
10. Power analysis of gated pipeline registers
11. The design and use of SimplePower: A cycle-accurate energy estimation tool