-
1
-
-
0347895367
-
Low power CMOS design
-
A. Chandrakasan, S. Sheng, and R. Brodersen, "Low power CMOS design", IEEE J. Solid-State Circuits 2, 4 (1992) 472-484.
-
(1992)
IEEE J. Solid-State Circuits
, vol.2
, Issue.4
, pp. 472-484
-
-
Chandrakasan, A.1
Sheng, S.2
Brodersen, R.3
-
2
-
-
0025502963
-
A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture
-
T. Hirose et al., "A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture", IEEE J. Solid-State Circuits SC-25 (1990) 1068-1074.
-
(1990)
IEEE J. Solid-State Circuits
, vol.SC-25
, pp. 1068-1074
-
-
Hirose, T.1
-
3
-
-
0027961632
-
A 400 Mhz, 300 mW, 8 Kb, CMOS SRAM macro with a current sensing scheme
-
M. Izumikawa et al., "A 400 Mhz, 300 mW, 8 Kb, CMOS SRAM macro with a current sensing scheme", IEEE Custom Integrated Circuits Conf., 1994, pp. 595-598.
-
(1994)
IEEE Custom Integrated Circuits Conf.
, pp. 595-598
-
-
Izumikawa, M.1
-
4
-
-
0029194648
-
Energy optimization of multi-level processor cache architectures
-
U. Ko, P. T. Balsara, and A. K. Nanda, "Energy optimization of multi-level processor cache architectures", ISLPD Symp. Proc., 1995, pp. 45-49.
-
(1995)
ISLPD Symp. Proc.
, pp. 45-49
-
-
Ko, U.1
Balsara, P.T.2
Nanda, A.K.3
-
5
-
-
0026254962
-
A 21-mW 4-Mb CMOS SRAM for battery operation
-
S. Murakami et al., "A 21-mW 4-Mb CMOS SRAM for battery operation", IEEE J. Solid-State Circuits SC-26, 11 (1991) 563-569.
-
(1991)
IEEE J. Solid-State Circuits
, vol.SC-26
, Issue.11
, pp. 563-569
-
-
Murakami, S.1
-
7
-
-
0029540358
-
Evaluation of architecture-level power estimation for CMOS RISC processors
-
T. Sato, Y. Ootaguro, M. Nagamatsu, and H. Tago, "Evaluation of architecture-level power estimation for CMOS RISC processors", IEEE Symp. on Low Power Electronics Proc., 1995, pp. 44-45.
-
(1995)
IEEE Symp. on Low Power Electronics Proc.
, pp. 44-45
-
-
Sato, T.1
Ootaguro, Y.2
Nagamatsu, M.3
Tago, H.4
-
8
-
-
0342495623
-
A 9 ns 16 Mb CMOS SRAM with off-set reduced current sense amplifier
-
Feb.
-
K. Seno et al., "A 9 ns 16 Mb CMOS SRAM with off-set reduced current sense amplifier", ISSCC Digest of Technical Papers, Feb. 1993, pp. 248-249.
-
(1993)
ISSCC Digest of Technical Papers
, pp. 248-249
-
-
Seno, K.1
-
9
-
-
0029340286
-
A low-power synchronous SRAM macrocell with latch-type fast sense circuits
-
N. Shibata and M. Watanabe, "A low-power synchronous SRAM macrocell with latch-type fast sense circuits", IEICE Trans. Electronics E78-C, 7 (1995).
-
(1995)
IEICE Trans. Electronics
, vol.E78-C
, Issue.7
-
-
Shibata, N.1
Watanabe, M.2
-
10
-
-
0029504791
-
An automatic-power-save cache memory for low-power RISC processors
-
Y. Shimazaki et al., "An automatic-power-save cache memory for low-power RISC processors", IEEE Symp. on Low Power Electronics Proc., 1995, pp. 58-59.
-
(1995)
IEEE Symp. on Low Power Electronics Proc.
, pp. 58-59
-
-
Shimazaki, Y.1
-
11
-
-
35048834531
-
Bus-invert coding for low power I/O
-
M. R. Stan and W. P. Burleson, "Bus-invert coding for low power I/O", IEEE Trans. VLSI Systems 3, 1 (1995) 49-58.
-
(1995)
IEEE Trans. VLSI Systems
, vol.3
, Issue.1
, pp. 49-58
-
-
Stan, M.R.1
Burleson, W.P.2
-
14
-
-
0028591619
-
A dynamic current-offset calibration (DCC) sense amplifier with fish-bone shaped mid-line (FBB) for high density SRAMs
-
J. Takahashi, T. Wada, and Y. Nishimura, "A dynamic current-offset calibration (DCC) sense amplifier with fish-bone shaped mid-line (FBB) for high density SRAMs", 1994 IEEE Symp. on VLSI Circuits Digest of Technical Papers, 1994, pp. 115-116.
-
(1994)
1994 IEEE Symp. on VLSI Circuits Digest of Technical Papers
, pp. 115-116
-
-
Takahashi, J.1
Wada, T.2
Nishimura, Y.3
-
15
-
-
0028585577
-
Automatic voltage-swing reduction (AVR) scheme for ultra low power DRAMs
-
M. Tsukude, M. Hirose, S. Tomishima, and T. Tsuruda, "Automatic voltage-swing reduction (AVR) scheme for ultra low power DRAMs", 1994 IEEE Symp. on VLSI Circuits Digest of Technical Papers, 1994.
-
(1994)
1994 IEEE Symp. on VLSI Circuits Digest of Technical Papers
-
-
Tsukude, M.1
Hirose, M.2
Tomishima, S.3
Tsuruda, T.4
-
17
-
-
0008576108
-
A 64 Kb full CMOS RAM with divided word line structure
-
M. Yoshimoto et al., "A 64 Kb full CMOS RAM with divided word line structure", ISSCC Digest of Technical Papers, 1983.
-
(1983)
ISSCC Digest of Technical Papers
-
-
Yoshimoto, M.1
-
18
-
-
0020830611
-
A divided word-line structure in the static RAM and its application to a 64 K full CMOS RAM
-
M. Yoshimoto et al., "A divided word-line structure in the static RAM and its application to a 64 K full CMOS RAM", IEEE J. Solid-State Circuits SC-18 (1983) 479-485.
-
(1983)
IEEE J. Solid-State Circuits
, vol.SC-18
, pp. 479-485
-
-
Yoshimoto, M.1
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