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Volumn 7, Issue 1, 1997, Pages 49-67

Power-area trade-offs in divided word line memory arrays

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EID: 0012794394     PISSN: 02181266     EISSN: None     Source Type: Journal    
DOI: 10.1142/S021812669700005X     Document Type: Article
Times cited : (7)

References (18)
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  • 3
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  • 4
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  • 5
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    • A 21-mW 4-Mb CMOS SRAM for battery operation
    • S. Murakami et al., "A 21-mW 4-Mb CMOS SRAM for battery operation", IEEE J. Solid-State Circuits SC-26, 11 (1991) 563-569.
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    • Feb.
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    • Seno, K.1
  • 9
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    • Shibata, N.1    Watanabe, M.2
  • 10
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    • Shimazaki, Y.1
  • 11
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    • Bus-invert coding for low power I/O
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  • 14
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    • (1994) 1994 IEEE Symp. on VLSI Circuits Digest of Technical Papers , pp. 115-116
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  • 17
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  • 18
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.