메뉴 건너뛰기




Volumn 17, Issue 6, 1997, Pages 40-47

M32R/D-integrating dram and microprocessor

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL STORAGE; MICROPROCESSOR CHIPS; SEMICONDUCTOR STORAGE;

EID: 0031270287     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.641595     Document Type: Article
Times cited : (26)

References (10)
  • 1
  • 2
    • 3843110289 scopus 로고    scopus 로고
    • Performance Evaluation of a Microprocessor with On-Chip DRAM and High Bandwidth Internal Bus
    • IEEE
    • S. Iwata et al., "Performance Evaluation of a Microprocessor with On-Chip DRAM and High Bandwidth Internal Bus," Proc. Custom Integrated Circuits Conf., IEEE, 1996, pp. 13.3.1-13.3.4.
    • (1996) Proc. Custom Integrated Circuits Conf.
    • Iwata, S.1
  • 3
    • 0028600435 scopus 로고
    • A Novel Double Well with Buffer N- And P+ Gettering Layers for Suppression of Soft Error Rate (DOWNSER)
    • IEEE
    • S. Komori et al., "A Novel Double Well with Buffer N- and P+ Gettering Layers for Suppression of Soft Error Rate (DOWNSER)," Symp. VLSI Technology, Dig. Tech. Papers, IEEE, 1994, pp. 41-42.
    • (1994) Symp. VLSI Technology, Dig. Tech. Papers , pp. 41-42
    • Komori, S.1
  • 4
    • 84989448138 scopus 로고
    • A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications
    • IEEE
    • R. Uttecht et al., "A Four-Level-Metal Fully Planarized Interconnect Technology for Dense High Performance Logic and SRAM Applications," Proc. VLSI Multilevel Interconnection Conf., IEEE, 1991, pp. 20-26.
    • (1991) Proc. VLSI Multilevel Interconnection Conf. , pp. 20-26
    • Uttecht, R.1
  • 5
    • 84865953659 scopus 로고
    • Interconnect Technology for 16-Mbit DRAM and 0.5-μm CMOS Logic
    • IEEE
    • S. Luce et al., "Interconnect Technology for 16-Mbit DRAM and 0.5-μm CMOS Logic," Proc. VLSI Multilevel Interconnection Conf., IEEE, 1992, pp. 55-58.
    • (1992) Proc. VLSI Multilevel Interconnection Conf. , pp. 55-58
    • Luce, S.1
  • 6
    • 0027814242 scopus 로고
    • A Concurrent Operation CDRAM for Low Cost Multimedia
    • IEEE
    • A. Yamazaki et al., "A Concurrent Operation CDRAM for Low Cost Multimedia," Symp. VLSI Circuits, Tech. Papers, IEEE, 1993, pp. 61-62.
    • (1993) Symp. VLSI Circuits, Tech. Papers , pp. 61-62
    • Yamazaki, A.1
  • 7
    • 0029542956 scopus 로고
    • A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
    • IEEE
    • K. Dosaka et al., "A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU," Symp. VLSI Circuits, Tech. Papers, IEEE, 1995, pp. 19-20.
    • (1995) Symp. VLSI Circuits, Tech. Papers , pp. 19-20
    • Dosaka, K.1
  • 8
    • 0027229777 scopus 로고
    • 16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors
    • IEEE Computer Society Press, Los Alamitos, Calif.
    • J. Bunda et al., "16-Bit vs. 32-Bit Instructions for Pipelined Microprocessors," Proc. Int'l Symp. Computer Architecture, IEEE Computer Society Press, Los Alamitos, Calif., 1992, pp. 237-246.
    • (1992) Proc. Int'l Symp. Computer Architecture , pp. 237-246
    • Bunda, J.1
  • 9
    • 0031336171 scopus 로고    scopus 로고
    • JPEG Software Implementation Techniques Based on a 32-Bit RISC CPU
    • IEEE
    • T. Sakamoto et al., "JPEG Software Implementation Techniques Based on a 32-Bit RISC CPU," Proc Int'l Conf. Consumer Electronics, IEEE, 1997, pp. 88-89.
    • (1997) Proc Int'l Conf. Consumer Electronics , pp. 88-89
    • Sakamoto, T.1
  • 10
    • 3843052667 scopus 로고
    • ITE Television System Test Charts, digital standard picture, Inst. Image Information and Television Engineers, Tokyo
    • ITE Television System Test Charts, digital standard picture, Inst. Image Information and Television Engineers, Tokyo, 1985.
    • (1985)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.