Method of redundant clocking detection and power reduction at RT level design

International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 131-136

  Ohnishi, Mitsuhisa ^a   Yamada, Akihisa ^a   Noda, Hiroaki ^a   Kambe, Takashi ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DATA TRANSFER; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; REDUNDANCY; TIMING CIRCUITS;

POWER REDUCTION; REDUNDANT CLOCKING DETECTION; REGISTER TRANSFER (RT) LEVEL DESIGN; SYNCHRONOUS CIRCUITS;

SHIFT REGISTERS;

EID: 0030649428     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)