Double jeopardy in the nanoscale court?

IEEE Circuits and Devices Magazine

Volumn 19, Issue 1, 2003, Pages 28-34

  Chen, Qiang ^a   Bowman, Keith A ^b   Harrell, Evans M ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Inte Corp   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MATHEMATICAL MODELS; NANOTECHNOLOGY; PERMITTIVITY; POISSON EQUATION; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE;

CONDUCTIVE CHANNEL; ELECTROSTATIC POTENTIAL; SHORT CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0037235405     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/MCD.2003.1175105     Document Type: Article

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