1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 270-271+466+263

  Narendra, Siva ^a   Haycock, Matthew ^a   Govindarajulu, Venkatesh ^a   Erraguntla, Vasantha ^a   Wilson, Howard ^a   Vangal, Sriram ^a   Pangal, Amaresh ^a   Seligman, Erik ^a   Nair, Raj ^a   Keshavarzi, Ali ^a   Bloechel, Bradley ^a   Dermer, Gregory ^a   Mooney, Randy ^a   Borkar, Nitin ^a   Borkar, Shekhar ^a   Vivek De, ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; ROUTERS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

COMMUNICATIONS ROUTER;

CMOS INTEGRATED CIRCUITS;

EID: 0036107956     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. 3.2 GHz 6.4 Gb/s per wire signaling in 0.18 μm CMOS
2. A 28.5 GB/s CMOS non-blocking router for terabits/s connectivity between multiple processors and peripheral I/O nodes
3. A sub-0.1 μm circuit design with substrate-over-biasing
4. A CMOS band-gap reference circuit with sub-1 V operation
5. T CMOS