A 2 5 GHz 32 b integer-execution core in 130 nm dual-VT CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 412-413+478+409

  Vangal, S ^a   Borkar, N ^a   Seligman, E ^a   Govindarajulu, V ^a   Erraguntla, V ^a   Wilson, H ^a   Pangal, A ^a   Veeramachaneni, V ^a   Anders, M ^a   Tschanz, J ^a   Ye, Y ^a   Somasekhar, D ^a   Bloechel, B ^a   Dermer, G ^a   Krishnamurthy, R ^a   Narendra, S ^a   Stan, M ^a   Thompson, S ^a   De, V ^a   Borkar, S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BUFFER CIRCUITS; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; MOS DEVICES; SIGNAL GENERATORS;

STACK NODE PRECONDITIONING (SNP);

CMOS INTEGRATED CIRCUITS;

EID: 0036106120     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A 6.5 GHz 130 nm single-ended dynamic ALU and instruction scheduler loop
2. Comparative delay, noise and energy of high-performance domino adders with stack node preconditioning
3. Comparative delay and energy of single edgetriggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors