Top contacts for vertical double-gate MOSFETs

Microelectronic Engineering

Volumn 64, Issue 1-4, 2002, Pages 465-471

  Moers, J ^a   Trellenkamp, St ^a   Goryll, M ^a   Marso, M ^a   Van Der Hart, A ^a   Hogg, S ^a   Mantl, S ^a   Kordos P ^a   Luth H ^a  

^a FORSCHUNGSZENTRUM JÜLICH   (Germany)

Author keywords

CMP; Double gate MOSFET; Nanotechnology; Silicon devices; Vertical MOSFET

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); NANOTECHNOLOGY; SEMICONDUCTING SILICON; SUBSTRATES;

SILICON DEVICES;

MOSFET DEVICES;

EID: 0036776666     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(02)00822-5     Document Type: Conference Paper

References (11)

1. CMOS scaling into the nanometer regime
2. Vertical double-gate MOSFET based on epitaxial growth by LPCVD
3. A comparative study of advanced MOSFET concepts
4. Silicon-on-nothing (SON) - An innovative process for advanced CMOS
5. Scaling the MOS transistor below 0.1 μm: Methodology, device structures and technology requirements
6. Beyond the conventional MOSFET
7. Self-aligned (top and bottom) double-gate MOSFET with a 25-nm thick silicon channel
8. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy
9. FinFET - A self-aligned double-gate MOSFET scalable to 20 nm
10. Nanoscale CMOS spacer FinFET for the terabit era