A DFT method for core-based systems-on-a-chip based on consecutive testability

Proceedings of the Asian Test Symposium

Volumn , Issue , 2001, Pages 193-198

  Yoneda, Tomokazu ^a   Fujiwara, Hideo ^a  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Consecutive testability; Consecutive transparency; Core based systems on a chip; Design for testability; Test access mechanism

Indexed keywords

DESIGN FOR TESTABILITY; INTEGER PROGRAMMING; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; LOGIC DESIGN;

CONSECUTIVE TESTABILITY; CONSECUTIVE TRANSPARENCY; CORE BASED SYSTEMS ON A CHIP; TEST ACCESS MECHANISM;

MICROPROCESSOR CHIPS;

EID: 0035704353     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Testing embedded-core based system chips
2. A unifying methodology for intellectual property and custom logic testing
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6. A low overhead design for testability and test generation technique for core-based systems-on-a-chip
7. A fast and low cost testing technique for core-based system-on-chip
8. Structural fault testing of embedded cores using pipelining