Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 244-251

  Visweswariah, Chandu ^a   Conn, Andrew R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DIGITAL CIRCUITS; ELECTRIC WIRE; FIELD EFFECT TRANSISTORS; OPTIMIZATION; REDUNDANCY; RESPONSE TIME (COMPUTER SYSTEMS);

DEGENERACY; STATIC CIRCUIT OPTIMIZATION; TIMING GRAPH MANIPULATION;

TIMING CIRCUITS;

EID: 0033351695     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)