Design methodology of the high performance large-grain polysilicon MOSFET

IEEE Transactions on Electron Devices

Volumn 49, Issue 5, 2002, Pages 795-801

  Jagar, Singh ^b   Wang, Hongmei ^c   Chan, Mansun ^a,b  

^a IEEE

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^c MICRON TECHNOLOGY INC   (United States)

Author keywords

3 D VLSI; Design methodology; Grain boundaries; MILC; Polysilicon; SOI material; Thin film transistor

Indexed keywords

CRYSTALLIZATION; MOSFET DEVICES; POLYSILICON; SEMICONDUCTING FILMS; SILICON ON INSULATOR TECHNOLOGY; THIN FILM TRANSISTORS; VLSI CIRCUITS;

METAL INDUCED LATERAL CRYSTALLIZATION; POLYSILICON ON INSULATOR FILM; POLYSILICON TRANSISTORS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036564641     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.998586     Document Type: Article

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