Post-CMOS processing for high-aspect-ratio integrated silicon microstructures

Journal of Microelectromechanical Systems

Volumn 11, Issue 2, 2002, Pages 93-101

  Xie, Huikai ^a,b   Erdmann, Lars ^b,c   Zhu, Xu ^a,b   Gabriel, Kaigham J ^a,b   Fedder, Gary K ^a,b  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c CARL ZEISS SMT AG   (Germany)

Author keywords

Complementary metal oxide semiconductor (CMOS) MEMS; Deep reactive ion etch (DRIE); Electrostatic spring; Inertial sensors

Indexed keywords

ADVANCED SILICON ETCH; DEEP SILICON BACKSIDE ETCH; ELECTRICAL ISOLATION; ELECTROSTATIC SPRING; HIGH ASPECT RATIO; INERTIAL SENSORS; PARASITIC CAPACITANCE; POST CMOS PROCESSING; PROOF MASS; THERMAL COEFFICIENT MISMATCH;

CMOS INTEGRATED CIRCUITS; ELECTROSTATIC DEVICES; INTEGRATED CIRCUIT LAYOUT; MICROSTRUCTURE; REACTIVE ION ETCHING; RESIDUAL STRESSES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SENSORS; SINGLE CRYSTALS; SPURIOUS SIGNAL NOISE; THIN FILMS;

MICROELECTROMECHANICAL DEVICES;

EID: 0036540106     PISSN: 10577157     EISSN: None     Source Type: Journal    
DOI: 10.1109/84.993443     Document Type: Article

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