0.25 μm merged bulk DRAM and SOI logic using patterned SOI

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 66-67

  Hannon, Robert ^a   Iyer, S Sundar Kumar ^a   Sadana, Devendra ^a   Rice, James P ^a   Ho, Herbert L ^a   Khan, Babar A ^a   Iyer, Subramanian S ^a  

^a Semiconductor Research and   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; LOGIC CIRCUITS; SILICON ON INSULATOR TECHNOLOGY;

PATTERNED WAFERS;

VLSI CIRCUITS;

EID: 0033714412     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)