Effects of build-up printed circuit board thickness on the solder joint reliability of a wafer level chip scale package (WLCSP)

IEEE Transactions on Components and Packaging Technologies

Volumn 25, Issue 1, 2002, Pages 3-14

  Lau, John H ^a,b   Lee, S W Ricky ^a,c  

^a IEEE   (United States)

^b AGILENT TECHNOLOGIES   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Creep of solders; Flip chip; Microvias; PCB; Reliability; Solder joint; WLCSP

Indexed keywords

CREEP; PRINTED CIRCUIT BOARDS; RELIABILITY; SHEAR STRENGTH; SOLDERED JOINTS; STRAIN; THERMAL EXPANSION; WSI CIRCUITS;

MICROVIAS;

CHIP SCALE PACKAGES;

EID: 0036505201     PISSN: 15213331     EISSN: None     Source Type: Journal    
DOI: 10.1109/6144.991169     Document Type: Article

References (27)

1. Wafer level chip scale packaging (WL-CSP): An overview
2. Manufacturing perspective of wafer level CSP
3. Fab integrated packaging (FIP): A new concept for high reliability wafer-level chip size packaging
4. Optimal structure of wafer level package for the electrical performance
5. 3)
6. Wafer level CSP using low cost electroless redistribution layer
7. Recent advances on a wafer-level flip chip packaging process
8. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblie
9. Nonlinear fracture mechanics analysis of wafer-level chip scale package solder joints with cracks
10. Fabrication of wafer level chip scale packaging for optoelectronic devices
11. Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis
12. Creep analysis of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag and 100 In lead-free solder joints and microvia build-up printed circuit board
13. Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability
14. A new thermal-fatigue life prediction model for wafer level chip scale package (WLCSP) solder joints
15. Overview of microvia technologies
16. Nonlinear-time-dependent analysis of micro via-in-pad substrates for solder bumped flip chip applications
17. Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints
18. Micro-mechanical deformation analysis of surface laminar circuit in organic flip-chip package: An experimental study