Wafer-level defect-based testing using enhanced voltage stress and statistical test data evaluation

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 683-692

  Quach, Minh ^a   Pham, Tuan ^a   Figal, Tim ^a   Kopitzke, Bob ^a   O'Neill, Pete ^b  

^a AGILENT TECHNOLOGIES   (United States)

^b AGILENT LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA PROCESSING; DEFECTS; ELECTRIC BREAKDOWN; FAILURE ANALYSIS; FIELD EFFECT TRANSISTORS; HOT CARRIERS; RELIABILITY; SILICON WAFERS; STATISTICAL METHODS;

ENHANCED VOLTAGE STRESS; LIFE FAILURE DEFECTS; LOW VOLTAGE SWEEP; STATISTICAL TEST DATA EVALUATION;

INTEGRATED CIRCUIT TESTING;

EID: 0036443153     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

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