4-um2 full-CMOS SRAM cell technology for 0.2-um high-performance logic LSIs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 11-12

  Takao, Y ^a   Sambonsugi, Y ^a   Watanabe, K ^a,a   Takatsuka, H ^a   Karasawa, T ^a   Kawamura, E ^a   Hashimoto, K ^a   Takagi, H ^a   Inoue, F ^a   Shimizu, H ^a   Yamazaki, T ^a   Goto, H ^a   Sugii, T ^a   Miyajima, M ^a   Aoyama, K ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); LOGIC CIRCUITS; LSI CIRCUITS;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0030705628     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)